The present invention relates to methods and systems for dubbing a data-compressed digital video signal on a record medium with the use of a digital video tape recorder (VTR), video disk recorder or the like.
Digital VTR's have been developed for broadcasting applications utilizing D1, D2 and D3 formats. In addition, various other formats have been proposed for consumer-use VTR's.
FIG. 1 provides a block diagram of a consumer-use digital VTR which carries out data compression through discrete cosine transformation (DCT) and variable length coding of data to be recorded. As shown in FIG. 1, an input analog component video signal (Y, R-Y, B-Y) is converted to a digital component video signal by means of A-D converter 1 and is then formed into data blocks by a block segmentation circuit 2 employing a frame memory. Each block of data is arranged as eight horizontal samples by eight vertical lines of a corresponding picture and is also referred to hereinafter as an 8.times.8 unit. The resultant data is shuffled and Y/C-multiplexed. Each of the 8.times.8 units is then discrete cosine transformed by a DCT circuit 3 to convert the data therein from the time domain into the frequency domain, so that each DCT converted block includes a DC component and one or more AC components. The discrete-cosine-transformed data is then re-quantized by an encoder 4 and variable-length encoded therein for data compression by a technique such as two-dimensional Huffman coding.
In the above-described system, the step width used in the re-quantization process is selected separately for each successive group of thirty DCT blocks, each such group also being referred to herein as a buffering unit, so that when the data is re-quantized the amount thereof will not exceed a certain level. Referring also to FIG. 2, each buffering unit is formed into a plurality of sync blocks, each including six blocks of data arranged successively as two luminance blocks Y, followed by a color component block C, followed in turn by a further two luminance blocks Y which then is followed by a final color component block C. It will be seen from FIG. 2 that each group of six blocks is provided with synchronization data (SYNC), identification data (ID) and auxiliary data (AUX),as well as quantization step size data (QNO) and parity data. Moreover, the data in each sync block is arranged as a sequence of ninety bytes. The data of each DCT block Y and C is further arranged to place the DC component thereof first, followed by a lowest frequency AC component which is followed in succession by further AC components of increasingly higher frequencies. The data of each DCT block is terminated by an end of block (EOB) code. Since the space provided for each of the DCT blocks is limited, any data which exceeds the predetermined limit of a respective block as shown in FIG. 2 (referred to as overflow data) is included in any available empty area of at least one other DCT block.
With reference again to FIG. 1, a framing circuit 5 serves to vertically align a plurality of buffering units as described above into a larger unit which is combined with an error correction code (ECC) by a parity generator 6. The data as thus constituted is then converted by means of a channel encoder 7 into serial form for recording.
When the data in serial form is reproduced, it is detected and converted to parallel form by means of a channel decoder 8 and then error-corrected by an ECC circuit 9. The error-corrected data is then separated into the variable-length code words of each block by a de-framing circuit 10 and subsequently decoded and de-quantized by a decoder 11. The resultant data is then inversely discrete cosine transformed by an inverse DCT circuit (IDCT) 12 to yield 8.times.8 unit blocks of time domain data.
The data blocks as thus reproduced are de-shuffled, Y/C demultiplexed and data-interpolated by a block desegmentation circuit 13 to recover the digital component video signal. Finally, the digital video signal is converted by a D/A converter 14 into a reproduction of the original analog component video signal to be output by the reproducing system of FIG. 1.
Data processing as carried out in the framing circuit 5 and de-framing circuit 10 of FIG. 1 will now be described in greater detail with reference to FIG. 3. As mentioned above, each DCT block includes a DC data component and one or more AC data components. The DC component of each block has a fixed word length, while the AC components are encoded as variable-length data. As shown at (1) of FIG. 3, the AC data of a representative DCT block includes 15 variable-length words, each AC component being indicated by an asterix [*], which designation is similarly employed throughout the present application to designate AC data. It will be appreciated that the number of variable-length words in the DCT blocks will vary from block to block. As illustrated at (2) of FIG. 3, the DCT blocks as shown at (1) of FIG. 3 are packed into a fixed-length word format by means of the framing circuit 5 of FIG. 1, in this example, as a sequence of 8-bit words, prior to recording.
When the data is reproduced, it is error-corrected by the ECC circuit 9 of FIG. 1. The byte length data supplied by the ECC circuit is illustrated, for example, at (3) of FIG. 3. As shown therein, an error bit is added to each 8 bit word by the ECC circuit 9 for indicating those bytes having erroneous data which cannot be corrected by the circuit 9. Each buffering unit with such error information attached is separated by the de-framing circuit 10 into valid data as well as variable-length code words which include data impossible to decode due to such errors. As indicated at (4) of FIG. 3, if an error should occur in an AC component *10 of the exemplary DCT block as reproduced, each of the higher frequency components *11 through *15 is likewise impossible to decode due the error in component *10. Based on the attached error information, the block de-segmenting circuit 13 carries out interpolation for purposes of error compensation.
To carry out dubbing with the digital VTR described above, three possible techniques, labelled respectively A, B and C as illustrated in FIG. 4, are described hereinafter. Technique A is an ordinary analog dubbing technique in which the analog output of D/A converter 14 is supplied to the input of A/D converter 1 of the recording system. Technique B is a digital dubbing technique in which a digital component output from the block de-segmenting circuit 13 is supplied via a digital interface (I/F) 15 to the input of the block segmentation circuit 2 of the recording system.
Technique C is a digital dubbing technique in which reproduced data subjected to error correction by the ECC circuit 9 and separated into variable-length code words by the de-framing circuit 10, are conveyed via a digital interface (I/F) 16 to the framing circuit 5 of the recording system of FIG. 4. Thereupon the data are rearranged in sync block format by the framing circuit 5, supplied with new parities by the parity generator 6 and then recorded.
The analog dubbing technique A mentioned above necessarily degrades image quality. Since technique B processes an uncompressed video signal, its transfer rate is relatively high (approximately 100 Mbps). Also, since the data is again subjected to DCT, it is possible that image quality degradation can result.
Although technique C provides a relatively low transfer rate because the video signal is compressed, the error information provided by the ECC circuit 9 to designate residual (that is, uncorrectable) errors is lost when the framing circuit 5 converts the data into the fixed-length, sync block format. Consequently, erroneous data will be decoded upon reproduction of data dubbed in this manner. In addition, errors occurring in the transmission path including that from the reproducing system to the recording system (for example, in the digital I/F 16) will be treated as valid data and decoded upon reproduction.
The following measures may be considered for alleviating the foregoing problem:
(1) error compensation by interpolation may be carried out by the digital I/F 16 or the ECC circuit 9; or PA1 (2) the data may be transmitted from the reproducing system to the recording system with a parity to be recorded therewith.
However, interpolation requires a frame memory. In addition, since the data to be processed has been variable-length encoded and formed into DCT blocks, all of the data in each DCT block in which an error has occurred must be replaced by interpolation, and only blocks which are error-free may be used for this purpose. Accordingly, otherwise valid data in a DCT block in which an error has occurred will be lost. Where an image is reproduced from a master tape, valid data from blocks containing errors (for example, an AC component having a frequency lower than a component represented by the erroneous data) may still be employed to produce an image. Consequently, a mismatch will occur between an image produced from such a master tape and one reproduced from a tape in this manner.
Transmission of the data with a parity for recording does not prevent accumulation of errors resulting from repeated dubbing operations. Such errors substantially impair the correction capability of the ECC circuit which can lead to image quality degradation.